Abstract: The paper presents an algorithm for embedded systems co-synthesis. The goal of the co-synthesis is to find the most cost-effective heterogenic architecture complying with execution time constraints. Additionally, presented methodology creates communication infrastructure for allocated and mapped processing elements with the use of Network-on-Chip (NoC) architecture. Dedicated topology along with pre-determined routing eliminate any communication contention. Experimental results prove superiority of our solution over state-of-the-art approaches on field of real-time embedded systems co-synthesis and custom NoC generation.
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